Frequency Range
2–20 GHz — full decade wideband coverage
Key Differentiator
+55 dBm OIP2 — 10–15 dB above typical wideband amplifiers
Technology
GaAs MMIC · 4×4 mm plastic QFN · 100% RF tested
Supply
+4 V single supply (3–5 V range) · 84 mA · No sequencing
Applications
Electronic Warfare · Direct-conversion receivers · Wideband radar
Compliance
REACH · RoHS · EAR99 · MSL 1 · HBM ESD Class 1A
Device image & functional block diagram · Single supply +Vd · RF In → Amp → RF Out
Functional Description
Single-ended RF In (Pin 3) → internally matched 50 Ω amplifier → single-ended RF Out (Pin 13). DC drain +Vd applied to Pin 17 via 0.1 µF bypass cap.
Internal Architecture
GaAs pHEMT gain cell optimized for OIP2. Internal 50 Ω matching at both ports — no external matching network required across 2–20 GHz.
No Sequencing Required
Apply +4 V and the device is operational immediately. No gate ramp, no negative supply, no turn-on sequence.
| Parameter | Typ | Unit | Notes |
|---|---|---|---|
| Output IP2 (OIP2) | +55 | dBm | 2–11 GHz · −25 dBm/tone · 1 MHz spacing — primary spec |
| Small Signal Gain | 19 | dB | Flat 2–20 GHz |
| Noise Figure | 4.2 | dB | 2–20 GHz |
| Output P1dB | +13.7 | dBm | 1 dB below Psat |
| Saturated Output Power | +14.7 | dBm | ~1 dB above P1dB |
| Output IP3 (OIP3) | +26 | dBm | 2–20 GHz · −15 dBm/tone |
| Input IP3 (IIP3) | +7.6 | dBm | OIP3 − Gain = 26 − 19 |
| Reverse Isolation | 35 | dB | 2–20 GHz |
| Supply Voltage Vd | +4 | V | Nominal (range 3–5 V) |
| Current Id | 84 | mA | No RF input |
| Part Number | Description | Package | ECCN | Status |
|---|---|---|---|---|
| ADM-11122PSM | 2–20 GHz Wideband High OIP2 Amplifier (IC) | Plastic QFN 4×4 mm | EAR99 | Released |
| EVB-ADM-11122P | Evaluation Board · 2.92 mm Female connectors | PCB Module | EAR99 | Released |
| Parameter | Fmin GHz | Fmax GHz | Min | Typ | Max | Unit | Conditions |
|---|---|---|---|---|---|---|---|
| Small Signal Gain | 2 | 20 | — | 19 | — | dB | Vd=4V, Id=84mA, Pin=−25dBm |
| Input Return Loss | 2 | 20 | — | 10 | — | dB | Vd=4V, Id=84mA, Pin=−25dBm |
| Output Return Loss | 2 | 20 | — | 10 | — | dB | Vd=4V, Id=84mA, Pin=−25dBm |
| Reverse Isolation | 2 | 20 | — | 35 | — | dB | Vd=4V, Id=84mA, Pin=−25dBm |
| Noise Figure | 2 | 20 | — | 4.2 | — | dB | Vd=4V, Id=84mA |
| Output P1dB | 2 | 20 | — | 13.7 | — | dBm | Vd=4V, Id=84mA |
| Saturated Output Power | 2 | 20 | — | 14.7 | — | dBm | Vd=4V, Id=84mA |
| Output IP2 (OIP2) | 2 | 11 | — | 55 | — | dBm | Vd=4V, Id=84mA, Pin=−25dBm/tone, 1 MHz spacing |
| Output IP3 (OIP3) | 2 | 20 | — | 26 | — | dBm | Vd=4V, Id=84mA, Pin=−15dBm/tone, 1 MHz spacing |
| Input IP3 (IIP3) | 2 | 20 | — | 7.6 | — | dBm | Vd=4V, Id=84mA, Pin=−15dBm/tone, 1 MHz spacing |
| Current Id | — | — | — | 84 | — | mA | Vd=4V, no RF input |
| Parameter | Rating | Unit |
|---|---|---|
| Max Operating Temperature | 85 | °C |
| Max Storage Temperature | 150 | °C |
| Max Junction Temp (MTTF > 1E6 hr) | 175 | °C |
| Min Operating Temperature | −40 | °C |
| Min Storage Temperature | −65 | °C |
| Max Drain Current (with RF) | 134 | mA |
| Max Drain Voltage Vd | 6 | V |
| Max RF Input Power | +10 | dBm |
| Thermal Resistance θJC | 50 | °C/W |
| Parameter | Min | Nominal | Max | Unit |
|---|---|---|---|---|
| DC Drain Current Id (no RF) | 60 | 84 | 107 | mA |
| Ambient Temperature | −40 | +25 | +85 | °C |
| Supply Voltage Vd | 3 | 4 | 5 | V |
| Parameter | Details | Value |
|---|---|---|
| ESD | Human Body Model | HBM Class 1A · 250–500 V |
| Package | Plastic QFN, 20-lead | 4 × 4 mm |
| Moisture Sensitivity | MSL 1 | No baking required |
| Substrate | LCP (Liquid Crystal Polymer) | — |
| Lead Finish | Ni 0.5–2.0 µm / Pd 0.08–0.15 µm / Au ≥0.003 µm | RoHS |
Static curves (solid/dashed lines): PCHIP-interpolated from 16 WebPlotDigitizer datasets (100–155 data points each), sourced from Marki Microwave datasheet Rev. – (2026-03-27). Anchor verification vs spec table: all parameters within ±0.4 dB/dBm average error. This is the most accurate digitization achievable from the published datasheet.
Interactive bias slider (Vd 3–5V): Linear interpolation between PCHIP-fitted 4V/84mA and 5V/107mA curves. Physically approximate between the two characterized bias points — use for trend estimation only.
Temperature toggles (−40 / +25 / +85°C): +25°C curves match the PCHIP bias data exactly. ±40/±85°C curves are scaled from manufacturer temperature performance plots (gain-like temperature dependence assumed for parameters without digitized temp data).
Solid = 4V/84mA · Dashed = 5V/107mA · All at TA = +25°C
| Parameter | −40°C | +25°C | +85°C | Trend |
|---|---|---|---|---|
| Gain (typ. 4–18 GHz) | ~21 dB | ~19 dB | ~17 dB | Decreases ~2 dB/100°C — standard GaAs |
| Noise Figure (typ. 4–18 GHz) | ~3.5 dB | ~4.2 dB | ~5.0 dB | Increases with temperature — budget 1 dB margin |
All unlabeled pins = GND. Solder all GND pins and paddle to PCB ground plane.
| Pin | Signal | Description |
|---|---|---|
| Pin 3 | RF Input | 50 Ω match, DC shorted to GND internally. Add DC block if DC present on line. |
| Pin 13 | RF Output | 50 Ω match, DC shorted to GND internally. Add DC block if DC present on line. |
| Pin 17 | Vd Supply | +4 V nominal (3–5 V range). Requires 0.1 µF bypass cap <0.5 mm from pin. |
| GND Paddle | Ground / Thermal | Solder to flooded ground plane with multiple vias. Critical for thermal and OIP2 performance. |
| All others | GND | Pins 1,2,4,5,6–12,14,15,16,18,19,20 → PCB RF/DC ground plane. |
Package
4×4 mm · 20-lead plastic QFN · 0.8 mm pitch
Ground Paddle
2.20×2.20 mm exposed — solder to flooded ground plane
Recommended PCB
Rogers 4003 · 0.008" thick · ½ oz copper both sides
EVB Connectors
2.92 mm Female (RF IN & RF OUT) — non-removable
Simplest bias topology in class: 1 positive supply + 1 bypass capacitor. No gate bias, no negative supply, no sequencing. Total external BOM = 1 capacitor.
VD (+4V) → 0.1 µF bypass cap → Pin 17 · RF In on Pin 3 · RF Out on Pin 13 · All other pins to GND
DC Supply — Pin 17
Apply +4 V through a 0.1 µF bypass capacitor placed <0.5 mm from Pin 17. Range: 3–5 V. Nominal current: 84 mA. No sequencing or negative voltage required.
RF Input — Pin 3
Direct 50 Ω connection. Internally matched — no external matching network. Add a DC blocking cap only if DC voltage is present on the input transmission line.
RF Output — Pin 13
Direct 50 Ω connection. Same DC blocking rule. Add DC block if downstream circuitry has DC bias on the line.
Ground — Paddle + All GND Pins
Solder exposed paddle to flooded ground plane with ≥4 plated-through vias. Connect all 17 GND pins to same plane. Critical for OIP2 performance.
Audience
RF/microwave engineers and system integrators. Assumes basic VNA and spectrum analyser familiarity.
Required Equipment
VNA (≥20 GHz, 2.92 mm cal kit) · DC supply 0–6V/200 mA · Signal generators ×2 · Spectrum analyser (≥26 GHz) · Power meter · 40 GHz cables + attenuators
Time to RF
~15–30 min on EVB-ADM-11122P with a pre-calibrated bench. Budget 2 hours for full OIP2 characterisation sweep.
ESD — HBM Class 1A
250–500 V limit. Always: wrist strap + ESD mat + grounded tools before touching the IC or EVB.
Inspect Solder — Before Powering Up
This is the highest-leverage step for OIP2. A cold or incomplete paddle solder joint increases thermal resistance and creates parasitic inductance in the ground path, degrading OIP2 by 5–10 dB. Use X-ray inspection if available. On the EVB: inspect under the IC with a dental mirror or macro lens. Look for solder fillet continuity at the exposed edges of the paddle.
⇒ Reference: Marki app note on QFN paddle soldering for microwave ICs (RoHS solder, Rogers 4003 substrate).
Power Up — Quiescent Current Check (No RF)
Apply Vd = +4.0 V with no RF input. Measure Id with a series ammeter or via supply readback. Acceptable range: 60–107 mA (nominal 84 mA). The device has no sequencing requirement.
| Observed Id | Diagnosis | Action |
|---|---|---|
| 0 mA | Open circuit — Vd pin not connected, or fuse blown | Check Pin 17 continuity to supply |
| <50 mA | Partial bias — possible solder bridge to GND on supply path | Inspect PCB, check Vd rail |
| 60–107 mA | Normal operation | Proceed |
| >134 mA | Overcurrent — possible oscillation or shorts | Power down immediately, inspect |
| Oscillating/noisy | Parasitic oscillation — insufficient bypass capacitance | Add 1–10 µF bulk cap to supply rail |
Measure Small-Signal S-Parameters (VNA)
2-port VNA measurement, 2–20 GHz. Cal at the 2.92 mm connector faces on the EVB. Input power: −25 dBm (well below P1dB). Reference: PCHIP data from WebPlotDigitizer below.
| Parameter | Frequency | Typical | Concern threshold |
|---|---|---|---|
| S21 (Gain) | 2–20 GHz | 17.8–19.4 dB | <15 dB → paddle solder issue or oscillation |
| S11 (Input RL) | 2–20 GHz | 6–22 dB | <5 dB → connector/PCB mismatch |
| S22 (Output RL) | 2–20 GHz | 6–22 dB | <5 dB → load mismatch or oscillation |
| S12 (Isolation) | 2–20 GHz | 34–39 dB | <30 dB → possible oscillation risk |
Note: Gain is flat ±1.5 dB across 2–20 GHz at nominal bias — this is unusually good for a decade-bandwidth amplifier. If gain drops sharply at any frequency, suspect connector resonance.
Measure OIP2 — The Primary Specification
This requires two phase-coherent, independently adjustable signal generators, a combiner, and a high-dynamic-range spectrum analyser. Setup matters significantly — generator harmonics or LO leakage will corrupt the measurement.
Test Conditions (per datasheet)
- Pin = −25 dBm/tone (both generators)
- Tone spacing: 1 MHz (e.g. 5.000 + 5.001 GHz)
- Frequency range: 2–11 GHz
- Bias: Vd = 4V, Id = 84 mA
Measurement Setup
- Use a 6 dB hybrid combiner (not resistive — better port isolation)
- Add 10 dB pads between generators and combiner
- Calibrate spectrum analyser input: correct for cable loss, pad loss
- Turn on SA preamp if IM2 power is below −80 dBm
Common Measurement Errors
- Generator 2nd harmonic falls on IM2 frequency → use YIG-filtered source
- Poor combiner isolation → IM2 generated in generator, not DUT
- SA in compression → use 20+ dB attenuation at SA input
- Cable movement changes result → secure all RF connections
Tone spacing sensitivity: OIP2 is relatively insensitive to tone spacing for spacings >100 kHz. At very narrow spacings (<10 kHz), flicker noise converts to IM2 and degrades measured OIP2. Use 1 MHz spacing as specified.
Measure OIP3, P1dB, and Psat
| Test | Setup | Expected | Method |
|---|---|---|---|
| OIP3 | 2 tones, −15 dBm/tone, 1 MHz spacing | +26 dBm | Measure IM3 on SA. OIP3 = P_fund + ½(P_fund − P_IM3) |
| P1dB | Single CW tone, power sweep | +13.7 dBm | Plot Pout vs Pin; find 1 dB gain compression point |
| Psat | Single CW, drive into saturation | +14.7 dBm | Plateau on Pout vs Pin curve (~1 dB above P1dB) |
| NF | Y-factor method, hot/cold source | 4.2 dB | Connect calibrated noise source to input; NF meter or SA method |
Bias Optimisation for Your Application
Once functionality is confirmed at nominal bias, experiment across the 3–5 V range. Key trade-off: higher Vd increases P1dB and Psat at the cost of OIP2 and power consumption.
| Bias Point | Vd | Id typ | Gain | OIP2 (4 GHz) | P1dB | Pdiss | Best Use |
|---|---|---|---|---|---|---|---|
| Nominal | 4 V | 84 mA | 18.3–19.4 dB | ~63 dBm | 13.7 dBm | 336 mW | EW / direct-conversion — default |
| High bias | 5 V | 107 mA | 18.1–19.3 dB | ~61 dBm | ~16 dBm | 535 mW | Higher Pout needed; accept higher PDC |
| Low power | 3 V | ~60 mA | ~17 dB | Degraded | <12 dBm | 180 mW | Power-constrained; verify all specs at this bias |
Troubleshooting — Common Failure Modes
| Symptom | Most Likely Cause | Diagnostic / Fix |
|---|---|---|
| OIP2 5–15 dB below spec | Incomplete paddle solder / poor ground | X-ray inspection; reflow with more paste; verify ≥4 ground vias under paddle |
| Gain 3+ dB low | Wrong bias / oscillation / damaged part | Confirm Vd=4V, Id=84mA with no RF; check for oscillation with SA at output |
| High gain variation vs freq | PCB resonance / connector issue | Re-calibrate VNA; check connector torque (≤8 in-lb for 2.92 mm); inspect cable |
| Oscillation (ring on supply) | Insufficient bypass capacitance | Add 1–10 µF tantalum + 100 nF X7R on Vd rail; check bypass cap placement |
| Id too low (<50 mA) | Open Vd path / damaged part | Check Pin 17 continuity; verify bypass cap is not shorted |
| Measured OIP2 too high | Generator IM2 not from DUT | Block DUT input and re-measure — if IM2 remains, it's a generator/setup artifact |
| NF >6 dB at 4–18 GHz | Lossy input connector/cable | De-embed connector loss; verify Cal plane is at DUT input, not cable end |
⚡ Electronic Warfare
OIP2 is the figure of merit. Use 4V bias. Test OIP2 across full 2–11 GHz range, not just at one frequency. Verify OIP2 does not degrade >3 dB over −40 to +85°C — temperature variation of ~2 dBm per 60°C is typical. In EW receive chains, this device is best placed as the 2nd stage after a low-NF LNA. A 15 dB LNA in front drops system NF to ~1.7 dB while maintaining the +55 dBm OIP2.
📡 Direct-Conversion Receivers
The critical concern is baseband IM2: two in-band blockers at f₁ and f₂ generate IM2 at |f₁−f₂| — falling directly at baseband, unfilterable. Highest-risk scenario: strong adjacent-channel signals at ±1–100 MHz offset. With OIP2 = +55 dBm and blockers at −30 dBm input, IM2 at baseband is −175 dBm — negligible. Verify that the preceding LNA also has adequate OIP2; cascaded OIP2 is dominated by the weakest stage.
🎯 Wideband Radar
For wideband radar receive chains, the relevant linearity metric is typically OIP3 (for Doppler sidelobes) rather than OIP2. OIP3 = +26 dBm across 2–20 GHz is moderate — use the Linearity Chain Budget tool (Design Tools tab) to verify 3rd-order SFDR meets your dynamic range requirement. NF = 4.2 dB is acceptable as a 2nd/3rd-stage amplifier behind a ~1.5 dB LNA.
In zero-IF and direct-sampling architectures, two blockers at f₁ and f₂ produce an IM2 product at |f₁−f₂|. This falls directly at baseband and cannot be filtered out. OIP2 is the key figure of merit.
At nominal bias (Pin = −25 dBm/tone, Gain = 19 dB):
Pout = Pin + Gain = −25 + 19 = −6 dBm (per tone at output)
IM2_out = 2 × Pout − OIP2 = 2×(−6) − 55 = −67 dBm
IM2 suppression = Pout − IM2_out = −6 − (−67) = 61 dBcFor true 2nd-order SFDR in 1 MHz noise bandwidth:
N_floor = kT + NF + 10·log(BW) = −174 + 4.2 + 60 = −109.8 dBm/MHz
SFDR₂ = OIP2 − N_floor = 55 − (−109.8) = 164.8 dB·Hz²/³ (or ~84 dB in 1 MHz BW)Note: SFDR₂ = OIP2 − N_floor uses input-referred noise floor with output-referred OIP2, which is the standard device-level definition (Pozar §10.3). Both quantities are device specs measured at the same reference port pair.
This device trades OIP3 for OIP2. Know when to use it:
- OIP2 = +55 dBm — Exceptional (typical wideband MMIC: +40–45 dBm). Peaks ~63 dBm at 3 GHz, rolls to ~46 dBm at 11 GHz.
- OIP3 = +26 dBm — Good gain block performance (IIP3 = OIP3 − Gain ≈ 7 dBm*)
- P1dB = +13.7 dBm — Keep operating point ≥20 dB below P1dB for best OIP2 preservation
- IIP2 = OIP2 − Gain = 55 − 19 = +36 dBm — extremely high for a wideband MMIC
* Spec table lists IIP3 = +7.6 dBm (vs. 7.0 dBm derived from OIP3−Gain). The 0.6 dB delta is due to slight gain compression at the Pin=−15 dBm test power — physically self-consistent.
Nominal bias: P_diss = 4 V × 84 mA = 336 mW
TJ = TC + θJC × Pdiss = TC + 50 × 0.336 = TC + 16.8°CθJC = 50°C/W (junction-to-case, from spec). Case temperature TC depends on your PCB and mounting:
For MTTF > 1×10⁶ hours, keep TJ < 175°C (Max Junction Temp from spec).
- Chain position: 2nd/3rd stage after a low-NF LNA (1.5–2 dB NF). The ADM's NF contribution is suppressed by the LNA gain via Friis.
- Input drive: Keep tones ≤ −25 dBm input for best OIP2. Beyond P1dB − 20 dB backoff, OIP2 degrades rapidly.
- Cascaded OIP2: One high-OIP2 stage early in the chain dominates system OIP2. Adding a second high-OIP2 stage provides diminishing returns — see Design Tools cascade calculator.
- OIP2 frequency range: Manufacturer specifies OIP2 only from 2–11 GHz. Performance above 11 GHz is not specified.
- OIP3-limited alternative: If 3rd-order linearity (OIP3) is the constraint, consider Marki ADM-9027PSM or similar (OIP3 = +25 dBm, lower NF, 2–20 GHz).
AID builds ML surrogate models that predict device behavior across PVT for components AID characterizes. AID's patented on-chip self-tuning technology maintains performance at temperature corners by dynamically adjusting bias — capabilities AID brings to new silicon designs. This datasheet demonstrates the AID AI Datasheet™ interactive format applied to a third-party device.
Contact: aianalog.co
All calculators use manufacturer-specified typical values at 4V/84mA, 25°C unless you override them. Results are engineering estimates — verify critical values with measurements. Formula references: Friis (1944) for cascaded NF; standard intercept-point linearity for SFDR (Pozar §10.3); JEDEC JESD51 for thermal.
🔬 = Engineering estimate | ⚠️ = Extrapolated or out of spec range | ✅ = Manufacturer data
Linearly interpolate between −40/+25/+85°C curves. Valid at Vd=4V/84mA only.
System NF of a prior stage followed by this amplifier. Formula: F_sys = F₁ + (F₂−1)/G₁.
IM2 output power and IM2 rejection ratio for two equal-power input tones. For SFDR vs. bandwidth, see the SFDR chart below.
TJ = TC + θJC×Pdiss. For TA-based: add θCA×Pdiss to your ambient temp to get TC first.
Operating point backoff from P1dB. Operate ≥20 dB below P1dB for best OIP2. Gain is editable — read your frequency from Charts tab.
System OIP2 when this amplifier follows another stage. Formula: 1/OIP2_sys = 1/OIP2₂ + G₂/OIP2₁ (output-referred). ADM-11122PSM is Stage 2 (G₂ = 19 dB fixed).
These tools are structured around the three listed applications. Formulae follow standard RF system engineering practice (Pozar, Maas, Razavi). OIP2 data valid 2–11 GHz only — see notice in each tool.
Shows fundamental tones, IM2 product, and noise floor. IM2 at |f₂−f₁| falls directly at baseband in direct-conversion systems.
Multi-stage cascade: edit stage parameters. ADM-11122PSM values are locked to spec. Cascaded NF (Friis), OIP2, OIP3, and SFDR computed automatically.
| Stage | Gain (dB) | NF (dB) | OIP2 (dBm) | OIP3 (dBm) | Label |
|---|
Min / Max / Mean gain and peak-to-peak ripple in your system bandwidth at 4V/84mA.
Noise temperature, output noise floor, and minimum detectable signal for your bandwidth.
SFDR₂ and SFDR₃ vs. noise bandwidth. SFDR₂ = OIP2 − N_floor; SFDR₃ = (2/3)×(OIP3 − N_floor). Standard device SFDR definition (Pozar §10.3).
AID AI Datasheet™ — Complete User Guide
How to get maximum engineering value from every tab, calculator, and chart in this interactive datasheet. Written for RF engineers and system integrators who designed or are evaluating the ADM-11122PSM.
Every data source in this datasheet is labeled with one of three badges so you always know the provenance and confidence level:
✅ Manufacturer Data
Directly from the Marki Microwave published datasheet (Rev –, 2026-03-27). Digitized from performance plots using WebPlotDigitizer at 1 GHz step resolution with PCHIP preprocessing. Anchor-checked against spec table values (all within ±0.5 dB).
Derived from published data using standard physics models (Friis, intercept-point theory, GaAs thermal scaling). Labeled throughout. Useful for initial design, but verify with your own measurements.
⚠️ Extrapolated / Out of Range
Performance outside the manufacturer's characterized range (e.g., Vd=3V, OIP2 above 11 GHz). Based on linear extrapolation or not available. Do not use for production design without characterization.
Overview
Device summary, application context, key differentiators vs. generic gain blocks, and a functional block diagram. Start here if you are evaluating this part for a new design.
Spec Tables
Complete electrical specifications (verbatim from PDF), absolute maximum ratings, recommended operating conditions, and package data. All values verified against Rev – datasheet.
Interactive Charts
Live bias slider (3–5 V) and temperature curve toggle (−40/+25/+85°C). Six interactive charts update in real time. Static comparison charts show 4V vs. 5V bias. See important notes below about what data is and is not from the PDF.
Pin Config
20-pin QFN pinout (X-ray view), port function table with DC equivalent circuits, and PCB layout guidance. Critical: solder all GND pins and the paddle to achieve specified OIP2.
Application
Recommended application circuit, bypass capacitor selection, PCB stackup guidance, and EW/direct-conversion system integration notes.
Bench Guide
Step-by-step bring-up procedure: quiescent current check, S-parameter measurement, OIP2 test setup, and troubleshooting table. Budget 2 hours for a full OIP2 sweep.
AI Insights
Physics-based analysis: correct IM2/SFDR equations, thermal budget with θJC vs. θJA distinction, linearity scorecard, and system design recommendations.
Design Tools
Eight interactive calculators: temperature estimator, Friis NF cascade, IM2/OIP2 calculator, corrected thermal budget, backoff/drive level, cascaded OIP2 chain, IM2 spectrum visualizer, and SFDR vs. bandwidth chart. See important caveats below.
| Chart | Source | Frequency Range | Temperature Data |
|---|---|---|---|
| Small-Signal Gain | ✅ PDF plot, digitized | 2–20 GHz | ✅ −40/+25/+85°C from PDF |
| Noise Figure | ✅ PDF plot, digitized | 2–20 GHz | ✅ −40/+25/+85°C from PDF |
| Output P1dB | ✅ PDF plot, digitized | 2–20 GHz | 🔬 Estimated (±1.5 dBm at ±60°C) |
| OIP2 | ✅ PDF plot, digitized | 2–11 GHz only | 🔬 Estimated (±2 dBm at ±65°C) |
| OIP3 | ✅ PDF plot, digitized* | 2–20 GHz | 🔬 Estimated (±2 dBm at ±60°C) |
| Psat | ✅ PDF plot, digitized | 2–20 GHz | 🔬 Estimated (±1.3 dBm at ±60°C) |
| S11 / S22 / Isolation | ✅ PDF plot, digitized | 2–20 GHz | Not shown (PDF has no temp data) |
* OIP3 chart data uses 1 dBm quantization from PDF plot. Re-digitization at 0.5 dBm resolution recommended before production use.
🌡️ Temperature Estimator
Formula: Linear interpolation between the three temperature anchor points (−40/+25/+85°C). Inputs: Ambient temperature slider. Valid only at Vd=4V/84mA. Gain and NF interpolations are from PDF; P1dB and OIP3 are engineering estimates.
📡 Cascaded Noise Figure (Friis)
Formula: F_sys = F₁ + (F₂−1)/G₁ where F = 10^(NF/10), G = 10^(Gain/10). Accuracy: Exact for two-stage cascade, independent of frequency. This is the classic Friis result — no approximations.
⚡ OIP2 / IM2 Calculator
Formulas: Pout = Pin + Gain; IM2_out = 2×Pout − OIP2; IM2 Suppression = Pout − IM2_out = OIP2 − Pout. Note: "IM2 Suppression" is the signal-to-IM2 ratio at the output, not SFDR. For SFDR vs. bandwidth, use the SFDR chart in Application Tools.
🌡️ Thermal Budget
Formula: TJ = TC + θJC × Pdiss where θJC = 50°C/W (from spec). Critical: TC is the case temperature (bottom of package), NOT ambient. For ambient-to-junction: TJ = TA + (θJC + θCA) × Pdiss. θCA depends on your PCB — typically 30–60°C/W for a well-soldered QFN on Rogers 4003 without forced air.
📊 P1dB Backoff / Drive Level
Formula: Pout = Pin + Gain (small-signal); Backoff = OP1dB − Pout. Note: "Gain" defaults to 19 dB (nominal spec). For bias-dependent gain, read the interpolated value from the Charts tab and enter manually. Backoff < 20 dB from P1dB will begin to degrade OIP2.
🔗 Cascaded OIP2 — Two Stages
Formula: 1/OIP2_sys = 1/OIP2₂ + G₂/(OIP2₁) where G₂ = ADM gain (linear). OIP2₁ and OIP2₂ are both output-referred. Stage 1 gain input sets Stage 2 gain only (ADM gain is fixed at typ. 19 dB). The formula is the standard voltage-wave two-stage cascade model.
⚡📡 IM2 Spectrum Visualizer
What it shows: Noise floor, IM2 product, and fundamental tone power on a simulated bar chart. OIP2 is looked up from digitized data at the entered frequency (2–11 GHz). Above 11 GHz: OIP2 is not manufacturer-specified — the tool shows N/A and uses no OIP2 estimate.
📈 SFDR vs. Bandwidth Chart
Formulas: SFDR₂ = OIP2 − N_floor where N_floor = −174 + NF + 10·log₁₀(BW_Hz). SFDR₃ = (2/3)×(OIP3 − N_floor). Reference temperature T=290K (IEEE standard, not 25°C). OIP2 is device output-referred; N_floor is at device input — this is the standard device-level SFDR definition.
Q: Why does IIP3 in the spec table (7.6 dBm) not equal OIP3 − Gain (26 − 19 = 7 dBm)?
A: OIP3 is tested at Pin = −15 dBm/tone. At that input power, the device has ~0.6 dB of gain compression vs. the small-signal test condition (Pin = −25 dBm). IIP3 = OIP3 − Gain_compressed ≈ 26 − 18.4 = 7.6 dBm. The 0.6 dB difference is physically consistent and not an error in the datasheet.
Q: Can I use OIP2 data above 11 GHz?
A: No manufacturer data exists above 11 GHz for OIP2. The device operates to 20 GHz and likely has OIP2 > 40 dBm based on the trend, but this is not characterized. This datasheet shows N/A for OIP2-dependent calculations above 11 GHz. If you need OIP2 above 11 GHz, you must characterize it yourself.
Q: My measured OIP2 is 8–10 dB below the +55 dBm spec. What is wrong?
A: The most common causes in decreasing order: (1) Incomplete paddle solder — a 5–10 dB OIP2 degradation is typical if the paddle is not fully soldered due to ground inductance; (2) Input power above spec — OIP2 degrades rapidly above Pin = −15 dBm; (3) Supply voltage outside 3–5 V range; (4) Insufficient bypass capacitance on Vd (must have 0.1 µF close to pin 17). See Bench Guide Step 1 for inspection procedure.
Q: Why is gain slightly higher at 3 V than at 4 V in the Charts tab?
A: The 3 V curve is a linear extrapolation below the 4 V data point (no 3 V characterization in the PDF). The extrapolation direction (slightly higher gain at 3 V) may be device-topology-specific behavior. Treat 3 V results as rough estimates only.
Q: The SFDR₂ value in the IM2 calculator says "IM2 Suppression" but the SFDR chart gives a different number. Which is right?
A: Both are correct but measure different things. "IM2 Suppression" (in the OIP2 calculator) = OIP2 − Pout = signal-to-IM2 ratio at the output. This does not depend on noise. "SFDR₂" (in the SFDR chart) = OIP2 − N_floor = the dynamic range from the noise floor to where IM2 emerges — this depends on bandwidth. For system link budget, use SFDR₂. For checking whether IM2 is above your noise floor, use the IM2 Spectrum Visualizer.
Q: What is the correct thermal model for this device?
A: TJ = TC + θJC × Pdiss where TC is measured case (package bottom) temperature and θJC = 50°C/W. If you can only measure ambient temperature TA, add your board-level thermal resistance θCA: TJ = TA + (θJC + θCA) × Pdiss. For Rogers 4003 with a well-soldered paddle and no forced air, θCA ≈ 40–60°C/W is a typical starting point. Simulate with your actual board stackup for a reliable estimate.
- AI Insights IM2 equation: Fixed. Now correctly uses output-referred Pout = Pin + Gain in the IM2 formula. Was: 2×Pin−OIP2. Now: 2×Pout−OIP2 = −67 dBm (not −105 dBm).
- IM2 calculator label: "SFDR" → "IM2 Suppression (dBc)". The correct SFDR₂ = OIP2−N_floor is in the SFDR vs. BW tool.
- Thermal calculator: Now uses TC (case temperature) as input, not TA. Added θCA guidance. Removed erroneous "no heat sink required" statement.
- OIP2 above 11 GHz: IM2 Visualizer and frequency query tool now show N/A above 11 GHz instead of defaulting to 55 dBm.
- Temperature curve labels: P1dB, OIP3, Psat temperature data labeled as "Est." (engineering estimates). Gain and NF temperature data confirmed from PDF.
- 3V extrapolation: Charts and live card labeled "extrapolated" at 3V bias. Warning added in User Guide.
- Cascade OIP2: G1 field label corrected to clarify it is context only; math uses G2 (ADM gain) correctly.
- Backoff calculator: Gain field made editable with note to use Charts tab for frequency/bias-specific value.
- AI Insights thermal: Corrected TJ formula example to use TA=85°C with θCA=40°C/W (realistic worst-case), not just θJC.